技術報告IEICE Transaction（電子情報通信学会英文論文誌／R.Ueno, N.Homma, T.Aoki and S.Morioka, “Hierarchical Formal Verification Combining Algebraic Transformation with PPRM Expansion and Its Application to Masked Cryptographic Processors”, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E100-A, No.7, pp.1396-1408, Jul. 2017.

Design Requirements and Implementation of Avionics System on Commercial Space Launch Vehicles Sumio MORIOKA Takahiro INAGAWA

技術報告日本航空宇宙学会・ISTS／Sumio Morioka, Satoshi Obana and Maki Yoshida, “Flight Demonstration Results of Information Theoretically Secure Wireless Communication on a Sounding Rocket MOMO,”Proc. of the 33rd International Symposium on Space Technology and Science (ISTS), Session J-2, 2022-j-06, Feb. 2022.

技術報告IEEE Design & Test／R.Ueno, N.Homma, T.Aoki and S.Morioka, “A Systematic Design Methodology of Formally-Proven Side-Channel-Resistant Cryptographic Hardware,” IEEE Design & Test ( Volume: 38, Issue: 3, June 2021), pp84-92

技術報告電子情報通信学会・英文論文誌／K.Sakamoto, K.Minematsu, N.Shibata, M.Shigeri, H.Kubo, Y.Funabiki, A.Bogdanov, S.Morioka, T.Isobe, “Tweakable TWINE: Building a tweakable block cipher on generalized feistel structure,” IEICE Transaction Vol.E103-A, No.12, pp.1629-1639

技術報告IEEE Transactions on Computers／R.Ueno, S.Morioka, N.Miura, K.Matsuda, M.Nagata, S.Bhasin, Y.Mathieu, T.Graba, J.L.Danger, N.Homma, “High Throughput/Gate AES Hardware Architectures Based on Datapath Compuression”, IEEE Trans. on Computers, Vol.69, Issue 4, pp.534-548, 2020.