DATE
IEEE Transactions on Computers／R.Ueno, S.Morioka, N.Miura, K.Matsuda, M.Nagata, S.Bhasin, Y.Mathieu, T.Graba, J.L.Danger, N.Homma, “High Throughput/Gate AES Hardware Architectures Based on Datapath Compuression”, IEEE Trans. on Computers, Vol.69, Issue 4, pp.534-548, 2020.
CATEGORY
【学会名】
IEEE Transactions on Computers
【タイトル】
R.Ueno, S.Morioka, N.Miura, K.Matsuda, M.Nagata, S.Bhasin, Y.Mathieu, T.Graba, J.L.Danger, N.Homma, “High Throughput/Gate AES Hardware Architectures Based on Datapath Compuression”, IEEE Trans. on Computers, Vol.69, Issue 4, pp.534-548, 2020.
【リンク】